1. Technical field
This invention relates to a MIS transistor with self-aligned grid and its manufacturing process. A MIS transistor is a transistor with a Metal-Insulator-Semiconductor type structure, for example such as MOS (Metal-Oxide-Semiconductor) transistors.
The invention is more particularly applicable to the manufacture of such transistors capable of operating in the hyper-frequency range, on a silicon substrate.
The invention is used for microelectronics applications for the manufacture of hyper-frequency and/or power circuits, for example for the production of circuits that can be used in the telecommunications field.
2. State of prior art
According to known art, hyper-frequency type components and circuits are made on gallium arsenide (AsGa) substrates, or on silicon (Si) substrates.
For cost reasons, circuits made on gallium arsenide substrates are usually not particularly complex and do not have a high integration density. Consequently the architecture of these circuits is not optimized for their compactness.
For example document (1), the reference of which is given at the end of this description, contains information about the production of hyper-frequency components on an AsGa substrate.
Furthermore, FIG. 1 attached also contains an example of a hyper-frequency component, in fact a MOS (Metal Oxide Semiconductor) transistor made on a silicon substrate.
The transistor in FIG. 1 comprises a source region 10, a channel region 12 and a drain region 14 defined in a silicon substrate 16. For example, the source and the drain are formed by implantation of n type or p type doping impurities and form regions with lower resistivity.
An insulating silicon oxide layer 18 is formed on the surface of substrate 16 and covers the source, channel and drain regions.
A non-through opening 20 is formed by etching in the oxide layer 18 approximately vertically in line with the channel region 12. A thin oxide layer 22 at the bottom of opening 20 forms a grid insulation. Finally, a grid 24 is formed in the opening 20.
The material in which the grid is formed, actually metal, has a low resistivity and thus enables high frequency operation of the resulting transistor.
The integration density of devices made according to FIG. 1 depends on the precision with which the opening 20, and then the grid 24, are aligned with respect to the channel 12 and the source and drain regions 10 and 14. This precision depends directly on the quality of manufacturing tools (particularly for alignment) used to make the semiconductor devices.
In a known manner, one way of increasing the compactness and integration density of circuits in order to make integrated circuits with MOS transistors on a silicon substrate, is to self-align the grid with respect to the source and drain regions.
It is assumed that the grid is self-aligned with respect to source and drain areas when the relative position of the grid and the source and drain areas are directly defined by the position of the grid itself, rather than being the result of an alignment of the means used (for example masks) to make these parts. In practice, self-alignment of the grid with respect to the source and drain regions is the result of a manufacturing process for the source and drain regions in which these regions are formed by implantation of impurities in the substrate using the grid, made earlier, as the implantation mask. The grid location thus precisely and automatically fixes the position of the source of the channel and the drain.
The processes for the formation of transistors with a grid self-aligned with the source and drain areas usually required a heat treatment carried out at high temperature. For example, in processes for making MOS on silicon transistors with a self-aligned grid, a heat treatment at a temperature of the order of 750xc2x0 C. or more is carried out after implantation of impurities, in order to activate the source and drain areas.
Furthermore a densification or creep of the insulation placed between the grid and the first metal interconnection level is done within an approximately identical temperature range.
Furthermore, as mentioned above, a grid material with a low resistivity has to be used so that the transistor can operate at high frequency. For guidance, when hyper-frequency type devices are being made, in other words devices that usually operate at a frequency exceeding 36 MHz, the grid material used to make the transistors must preferably have a resistivity of between about 1 and 10 xcexcxcexa9xc2x7cm.
In fact, materials with a resistivity within the given range are incapable of resisting the temperatures of the heat treatments applied in the processes described for manufacturing transistors with self-aligned grid. In particular, these materials are not capable of resisting temperatures equal to or exceeding 750xc2x0 C.
One material frequently used for making the grid for transistors with a self-aligned grid is polycrystalline silicon (poly Si). Polycrystalline silicon is capable of resisting the temperatures of heat treatments used when these transistors are being formed.
However, the resistivity of polycrystalline silicon is of the order of 103 xcexcxcexa9xc2x7cm, which is not compatible with envisaged applications of transistors in the hyper-frequency range. Furthermore, we do not know how to sufficiently reduce the resistivity of polycrystalline silicon so that transistors can operate in hyper-frequency.
Consequently, one purpose of this invention is to suggest a process for manufacturing MIS transistors with self-aligned grid, source and drain, and capable of operating within the hyper-frequency range.
Another purpose of the invention is to propose a process for manufacturing a compact transistor with interconnections in order to reduce the clearance of contacts with respect to the edge of grid conductors or interconnections.
Another purpose of the invention is to increase the integration density of the interconnections in a circuit comprising transistors with self-aligned grid, source and drain.
Another purpose of the invention is to propose a transistor designed to have a very high cutoff frequency.
Another purpose of the invention is to propose transistors compatible with the production of CMOS (complementary MOS) circuits with a high integration density.
More precisely, the purpose of the invention is a process for manufacturing MIS (Metal-Insulator-Semiconductor) transistors on a semiconductor substrate. The process is defined by claim 1. Another purpose of the invention is a MOS transistor such as that defined in claim 23.
The dummy grid made during the process performs two functions; initially, it is used to define the location of the source and drain regions in step b) and then to define the location of the final transistor grid made from a material with low resistivity. The coating of the dummy grid on its lateral flanks, after this dummy grid has been eliminated, forms a xe2x80x9cmoldxe2x80x9d for the final grid.
These characteristics guarantee automatic and perfectly precise alignment of the final grid with respect to the source and drain regions.
The final grid is formed from one or several materials. Each of these materials is chosen so as to have a low resistivity. For example, the resistivity of the materials may be chosen within a range varying from 1 to 10 xcexcxcexa9xc2x7cm.
According to one particular aspect of the invention, step a) may comprise:
formation on the substrate of a stack comprising an oxide layer called the pedestal layer, a polycrystalline silicon layer and a silicon nitride layer in this order, and
forming of the stack by etching to form the dummy grid with lateral flanks.
In this embodiment of the process, the dummy grid is composed of a thin silicon oxide layer, a polycrystalline or amorphous silicon layer, and then a silicon nitride layer, in this order.
The silicon nitride layer may be beneficially used to form the side coating of the dummy grid.
According to one particular aspect of the invention, step c) comprises:
deposition of a first electrically insulating layer of silicon oxide doped with phosphorus and then a second layer of silicon oxide that is not intentionally doped, the first and the second layers coating the dummy grid, and,
polishing of the first and second layers of silicon oxide, stopping on the dummy grid.
The silicon nitride layer included in the stack forming the dummy grid may advantageously be used to act as polishing stop layer.
According to another aspect of the invention, step b) may comprise:
a first implantation of a low dose of doping impurities using the dummy grid as an implantation mask,
the formation of spacers on the lateral flanks of the dummy grid,
a second implantation of doping impurities with a dose higher than the dose of the first implantation, using the dummy grid equipped with spacers as the implantation mask.
Due to this double implantation, a xe2x80x9cLow Doped Drainxe2x80x9d (LDD) type of source and drain architecture, necessary for long life of the components, can be made.
For example, the lateral spacers on the flanks of the dummy grid may be formed by:
an approximately conform deposit of a silicon oxide layer doped with phosphorus in order to coat the dummy grid, and,
anisotropic etching of the said layer to eliminate it above the dummy grid while maintaining part of the said layer on the lateral flanks of the dummy grid, this part forming lateral spacers.
It is assumed that the deposit is conform when it matches the shape of the surface of the support on which it is made. Due to the conform deposit of the layer of silicon oxide doped with phosphorus, this layer covers and is in contact not only on the lateral faces of the dummy grid, but also on the top of this grid. Anisotropic etching of the layer of silicon oxide doped with phosphorus can completely eliminate it on the top of the dummy grid while protecting the parts of the layer that will form the side spacers.
The transistor conform with the invention may be put in a circuit by connecting its terminals, formed by the source and drain regions and the grid, with other nearby components or transistors. Step b) in the process may also comprise silicidation of the source and drain regions in order to improve the quality of the contact between the interconnection lines used to form the circuit, and the source and drain regions. Silicidation is also self-aligned with respect to the dummy grid; it comprises a metal deposit which reacts by selectively forming an alloy (silicide) on exposed silicon areas.
According to one particular embodiment of step d) in the process, the process includes elimination by etching of silicon nitride and polycrystalline silicon layers in the dummy grid, the pedestal layer then forming an etching stop layer at the time of this etching.
The pedestal layer may also be eliminated in step d). In this case, a new insulating grid layer is formed before the final grid is made.
According to another specific aspect of the invention, step d) also includes partial etching of the first and second oxide layers before the formation of the final grid, in order to form a flare after the dummy grid has been eliminated.
The flare extends from the surface of the substrate and widens towards the upper surface of the first and second oxide layers.
Advantageously, the difference between the materials used to form the first and second layers is used beneficially to vary the etching speed on these layers. The flare can thus be configured to be in a particular shape. For example, the flare and particularly the final grid, may have a T-shaped cross-section.
Furthermore, step d) may also comprise partial elimination of the lateral spacers of the dummy grid. This elimination process, which can be done at the same time as the materials in the first and second oxide layers are etched, then contributes to shaping of the flare.
In one particular embodiment, manufacture of the final grid in step d) may include a successive and approximately conform deposit of a titanium nitride (TiN) layer and a tungsten (W) layer followed by flattening of these layers stopping on the electrical insulation layer. Due to the first layer of titanium nitride (TiN), it is guaranteed that there will be good bond of the tungsten (W) layer on a subjacent insulating grid layer. The grid insulation layer, for example made of silicon oxide, is preferably formed immediately before production of the final grid.
More generally, the material used in the final grid may advantageously by chosen with an extraction potential such that the Fermi level at equilibrium at the insulating transistor grid/channel interface are located at the mid-point of the prohibited band of the semiconductor.
The grid material may have a resistivity of between 1 xcexcxcexa9xc2x7cm and 10 xcexcxcexa9xc2x7cm, according to one advantageous example embodiment.
According to one particular aspect, the process according to the invention may also comprise the formation by doping of a channel region in the substrate before step a); the dummy grid being produced above the channel region.
Furthermore, the process may also be continued after step d) to include the following steps:
e) formation of contact points on the source and drain regions and on the grid,
f) metallization of contact points.
Contact points formed on the grid and the source and drain regions are advantageously formed through a layer of insulating material deposited on the free surface of the structure obtained after polishing the first and second layers of silicon oxide (or BPSG).
According to one improvement of the invention, the process for manufacturing a transistor with an insulated grid from a material with low resistivity, as described above, may also include the formation of a transistor with a silicon grid.
In this case, the steps of the process may be continued to include:
step a) includes the formation of a stack on the substrate, comprising an oxide layer called the pedestal layer, a polycrystalline or amorphous silicon layer, and a silicon nitride layer in order and in at least one first region, and comprising an oxide layer called the pedestal layer, the polycrystalline or amorphous silicon layer, a layer of silicon oxide called an intermediate layer, and the silicon nitride layer, in at least one second region; and shaping of the stack by etching to produce the dummy grid with lateral flanks in the first region and at least one grid called a silicon grid in the second region,
step b) includes the formation of a source region self-aligned on the dummy grid and a drain region self-aligned on the silicon grid region,
step c) includes lateral coating of the dummy grid and the silicon grid with at least one electrically insulating material,
step c) is preceded by elimination of silicon nitride layer on the silicon grid in the second region, elimination of the pedestal layer around the dummy grid and the silicon grid, and elimination of the intermediate silicon oxide layer,
step d) includes formation of a protection layer covering the silicon grid while the dummy grid is being eliminated, in the second region.
Advantageously, layers or parts common to transistors with a low resistivity grid and a transistor with a silicon grid are made simultaneously in the first and second regions.
Although the description is limited essentially to the manufacture of a single transistor with a low resistivity grid (with a metal grid) and a single silicon grid transistor, it can be understood that the process is applicable to simultaneous production of several transistors of either of the two types mentioned.
According to one particular embodiment of the invention, after the pedestal layer and the intermediate layer have been eliminated and before step c) is carried out, a self-aligned silicidation of the source and drain regions, and the polycrystalline or amorphous silicon layer in the silicon grid, can be carried out.
Silicidation can improve the contact on the source, drain and grid regions.
Furthermore, a thin layer of silicon nitride may be placed on the silicided regions, and particularly the silicided source and drain regions, in order to protect them.
This operation is applicable to grid transistors with a grid made of a low resistivity material and silicon grid transistors. In the latter case, the silicon nitride layer is also in contact with the silicide formed in the polycrystalline or amorphous silicon layer in the grid.
Finally, according to one advantageous aspect of the process for concurrent manufacturing of the transistors with the two types of grid mentioned above, the lateral coating of the dummy grid and the silicon grid in step c) may comprise:
deposition as mentioned above of a first electrically insulating layer made of silicon oxide doped with phosphorus and then a second electrically insulating layer of silicon oxide not intentionally doped, the first and second layers coating the dummy grid and the silicon grid, and,
polishing of the first and second silicon oxide layers stopping on the dummy grid, a thin layer of silicon oxide doped with phosphorus being kept on the polycrystalline or amorphous silicon layer of the silicon grid while this polishing is being done.
The main function of the thin layer of doped silicon oxide preserved on the layer of polycrystalline or amorphous silicon in the silicon grid is to protect the silicon grid when the silicon nitride layer on the dummy grid is being eliminated and when the dummy itself is being eliminated.
Other characteristics and advantages of the invention will become clear in the following description with reference to the figures in the attached drawings, given for purely illustrative and non-restrictive purposes.